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Date: Mon, 15 Sep 2025 13:24:18 +0400
Subject: [PATCH] arm64: dts: qcom: ipq5018: add QUP3 I2C node
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To: Bjorn Andersson <andersson@kernel.org>,
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Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
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From: George Moussalem <george.moussalem@outlook.com>

From: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>

Add node to support I2C bus inside of IPQ5018.

Signed-off-by: Vandhiadevan Karunamoorthy <vkarunam@codeaurora.org>
Signed-off-by: George Moussalem <george.moussalem@outlook.com>
---
 arch/arm64/boot/dts/qcom/ipq5018.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)


---
base-commit: b0971d2008c644b9064d968d440fb9f44606d90c
change-id: 20250911-ipq5018-i2c-0a0fa1762818

Best regards,

--- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi
@@ -504,6 +504,21 @@
 			status = "disabled";
 		};
 
+		blsp1_i2c3: i2c@78b7000 {
+			compatible = "qcom,i2c-qup-v2.2.1";
+			reg = <0x078b7000 0x600>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
+				 <&gcc GCC_BLSP1_AHB_CLK>;
+			clock-names = "core", "iface";
+			clock-frequency = <400000>;
+			dmas = <&blsp_dma 9>, <&blsp_dma 8>;
+			dma-names = "tx", "rx";
+			status = "disabled";
+		};
+
 		qpic_bam: dma-controller@7984000 {
 			compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
 			reg = <0x07984000 0x1c000>;
