[TASKMGR] et-EE.rc is better this way and with less changes

to existing translations.

base/applications/taskmgr/lang/et-EE.rc

@@ -131,7 +131,7 @@ BEGIN
         MENUITEM "Lõpeta protsessi&puu", ID_PROCESS_PAGE_ENDPROCESSTREE
         MENUITEM "&Silu", ID_PROCESS_PAGE_DEBUG
         MENUITEM SEPARATOR
-        POPUP "Määra &prioriteet"
+        POPUP "Mää&ra prioriteet"
         BEGIN
             MENUITEM "&Reaalajas", ID_PROCESS_PAGE_SETPRIORITY_REALTIME
             MENUITEM "&Kõrge", ID_PROCESS_PAGE_SETPRIORITY_HIGH
@@ -142,7 +142,7 @@ BEGIN
         END
         MENUITEM "Määra &ühtivus...", ID_PROCESS_PAGE_SETAFFINITY
         MENUITEM SEPARATOR
-        MENUITEM "P&roperties", ID_PROCESS_PAGE_PROPERTIES
+        MENUITEM "Prop&erties", ID_PROCESS_PAGE_PROPERTIES
         MENUITEM "&Open File Location", ID_PROCESS_PAGE_OPENFILELOCATION
     END
 END

dll/win32/shell32/shlfolder.cpp

@@ -241,8 +241,9 @@ HRESULT SHELL32_CompareDetails(IShellFolder2* isf, LPARAM lParam, LPCITEMIDLIST
     SHELLDETAILS sd;
     WCHAR wszItem1[MAX_PATH], wszItem2[MAX_PATH];
     HRESULT hres;
+    UINT col = LOWORD(lParam); // Column index without SHCIDS_* flags
 
-    hres = isf->GetDetailsOf(pidl1, lParam, &sd);
+    hres = isf->GetDetailsOf(pidl1, col, &sd);
     if (FAILED(hres))
         return MAKE_COMPARE_HRESULT(1);
 
@@ -250,7 +251,7 @@ HRESULT SHELL32_CompareDetails(IShellFolder2* isf, LPARAM lParam, LPCITEMIDLIST
     if (FAILED(hres))
         return MAKE_COMPARE_HRESULT(1);
 
-    hres = isf->GetDetailsOf(pidl2, lParam, &sd);
+    hres = isf->GetDetailsOf(pidl2, col, &sd);
     if (FAILED(hres))
         return MAKE_COMPARE_HRESULT(1);
 

ntoskrnl/config/cmkcbncb.c

@@ -164,7 +164,7 @@ CmpGetNameControlBlock(IN PUNICODE_STRING NodeName)
         if (*p != OBJ_NAME_PATH_SEPARATOR)
         {
             /* Add it to the hash */
-            ConvKey = 37 * ConvKey + RtlUpcaseUnicodeChar(*p);
+            ConvKey = COMPUTE_HASH_CHAR(ConvKey, *p);
         }
 
         /* Next character */
@@ -701,7 +701,7 @@ CmpCreateKeyControlBlock(IN PHHIVE Hive,
         if (*p != OBJ_NAME_PATH_SEPARATOR)
         {
             /* Add this key to the hash */
-            ConvKey = 37 * ConvKey + RtlUpcaseUnicodeChar(*p);
+            ConvKey = COMPUTE_HASH_CHAR(ConvKey, *p);
         }
 
         /* Move on */

ntoskrnl/include/internal/amd64/ke.h

@@ -418,7 +418,7 @@ VOID Ki386InitializeLdt(VOID);
 VOID Ki386SetProcessorFeatures(VOID);
 VOID KiGetCacheInformation(VOID);
 VOID KiSetProcessorType(VOID);
-ULONG KiGetFeatureBits(VOID);
+ULONG64 KiGetFeatureBits(VOID);
 VOID KiInitializeCpuFeatures(VOID);
 #if DBG
 VOID KiReportCpuFeatures(IN PKPRCB Prcb);

ntoskrnl/ke/amd64/cpu.c

@@ -10,6 +10,8 @@
 /* INCLUDES *****************************************************************/
 
 #include <ntoskrnl.h>
+#include <x86x64/Cpuid.h>
+#include <x86x64/Msr.h>
 #define NDEBUG
 #include <debug.h>
 
@@ -145,56 +147,74 @@ KiSetProcessorType(VOID)
     KeGetCurrentPrcb()->CpuStep = (USHORT)Stepping;
 }
 
-ULONG
+/*!
+    \brief Evaluates the KeFeatureFlag bits for the current CPU.
+
+    \return The feature flags for this CPU.
+
+    \see https://www.geoffchappell.com/studies/windows/km/ntoskrnl/structs/kprcb/featurebits.htm
+
+    \todo
+     - KF_VIRT_FIRMWARE_ENABLED 0x08000000 (see notes from Geoff Chappell)
+     - KF_FPU_LEAKAGE 0x0000020000000000ULL
+     - KF_CAT 0x0000100000000000ULL
+     - KF_CET_SS 0x0000400000000000ULL
+*/
+ULONG64
 NTAPI
 KiGetFeatureBits(VOID)
 {
     PKPRCB Prcb = KeGetCurrentPrcb();
     ULONG Vendor;
-    ULONG FeatureBits = KF_WORKING_PTE;
-    CPU_INFO CpuInfo;
+    ULONG64 FeatureBits = 0;
+    CPUID_SIGNATURE_REGS signature;
+    CPUID_VERSION_INFO_REGS VersionInfo;
+    CPUID_EXTENDED_FUNCTION_REGS extendedFunction;
 
     /* Get the Vendor ID */
     Vendor = Prcb->CpuVendor;
 
     /* Make sure we got a valid vendor ID at least. */
-    if (!Vendor) return FeatureBits;
+    if (Vendor == CPU_UNKNOWN) return FeatureBits;
+
+    /* Get signature CPUID for the maximum function */
+    __cpuid(signature.AsInt32, CPUID_SIGNATURE);
 
     /* Get the CPUID Info. */
-    KiCpuId(&CpuInfo, 1);
+    __cpuid(VersionInfo.AsInt32, CPUID_VERSION_INFO);
 
     /* Set the initial APIC ID */
-    Prcb->InitialApicId = (UCHAR)(CpuInfo.Ebx >> 24);
+    Prcb->InitialApicId = (UCHAR)VersionInfo.Ebx.Bits.InitialLocalApicId;
 
     /* Convert all CPUID Feature bits into our format */
-    if (CpuInfo.Edx & X86_FEATURE_VME) FeatureBits |= KF_V86_VIS | KF_CR4;
-    if (CpuInfo.Edx & X86_FEATURE_PSE) FeatureBits |= KF_LARGE_PAGE | KF_CR4;
-    if (CpuInfo.Edx & X86_FEATURE_TSC) FeatureBits |= KF_RDTSC;
-    if (CpuInfo.Edx & X86_FEATURE_CX8) FeatureBits |= KF_CMPXCHG8B;
-    if (CpuInfo.Edx & X86_FEATURE_SYSCALL) FeatureBits |= KF_FAST_SYSCALL;
-    if (CpuInfo.Edx & X86_FEATURE_MTTR) FeatureBits |= KF_MTRR;
-    if (CpuInfo.Edx & X86_FEATURE_PGE) FeatureBits |= KF_GLOBAL_PAGE | KF_CR4;
-    if (CpuInfo.Edx & X86_FEATURE_CMOV) FeatureBits |= KF_CMOV;
-    if (CpuInfo.Edx & X86_FEATURE_PAT) FeatureBits |= KF_PAT;
-    if (CpuInfo.Edx & X86_FEATURE_DS) FeatureBits |= KF_DTS;
-    if (CpuInfo.Edx & X86_FEATURE_MMX) FeatureBits |= KF_MMX;
-    if (CpuInfo.Edx & X86_FEATURE_FXSR) FeatureBits |= KF_FXSR;
-    if (CpuInfo.Edx & X86_FEATURE_SSE) FeatureBits |= KF_XMMI;
-    if (CpuInfo.Edx & X86_FEATURE_SSE2) FeatureBits |= KF_XMMI64;
+    if (VersionInfo.Edx.Bits.VME) FeatureBits |= KF_CR4;
+    if (VersionInfo.Edx.Bits.PSE) FeatureBits |= KF_LARGE_PAGE | KF_CR4;
+    if (VersionInfo.Edx.Bits.TSC) FeatureBits |= KF_RDTSC;
+    if (VersionInfo.Edx.Bits.CX8) FeatureBits |= KF_CMPXCHG8B;
+    if (VersionInfo.Edx.Bits.SEP) FeatureBits |= KF_FAST_SYSCALL;
+    if (VersionInfo.Edx.Bits.MTRR) FeatureBits |= KF_MTRR;
+    if (VersionInfo.Edx.Bits.PGE) FeatureBits |= KF_GLOBAL_PAGE | KF_CR4;
+    if (VersionInfo.Edx.Bits.CMOV) FeatureBits |= KF_CMOV;
+    if (VersionInfo.Edx.Bits.PAT) FeatureBits |= KF_PAT;
+    if (VersionInfo.Edx.Bits.DS) FeatureBits |= KF_DTS;
+    if (VersionInfo.Edx.Bits.MMX) FeatureBits |= KF_MMX;
+    if (VersionInfo.Edx.Bits.FXSR) FeatureBits |= KF_FXSR;
+    if (VersionInfo.Edx.Bits.SSE) FeatureBits |= KF_XMMI;
+    if (VersionInfo.Edx.Bits.SSE2) FeatureBits |= KF_XMMI64;
 
-    if (CpuInfo.Ecx & X86_FEATURE_SSE3) FeatureBits |= KF_SSE3;
-    //if (CpuInfo.Ecx & X86_FEATURE_MONITOR) FeatureBits |= KF_MONITOR;
-    //if (CpuInfo.Ecx & X86_FEATURE_SSSE3) FeatureBits |= KF_SSE3SUP;
-    if (CpuInfo.Ecx & X86_FEATURE_CX16) FeatureBits |= KF_CMPXCHG16B;
-    //if (CpuInfo.Ecx & X86_FEATURE_SSE41) FeatureBits |= KF_SSE41;
-    //if (CpuInfo.Ecx & X86_FEATURE_POPCNT) FeatureBits |= KF_POPCNT;
-    if (CpuInfo.Ecx & X86_FEATURE_XSAVE) FeatureBits |= KF_XSTATE;
+    if (VersionInfo.Ecx.Bits.SSE3) FeatureBits |= KF_SSE3;
+    if (VersionInfo.Ecx.Bits.SSSE3) FeatureBits |= KF_SSSE3;
+    if (VersionInfo.Ecx.Bits.CMPXCHG16B) FeatureBits |= KF_CMPXCHG16B;
+    if (VersionInfo.Ecx.Bits.SSE4_1) FeatureBits |= KF_SSE4_1;
+    if (VersionInfo.Ecx.Bits.XSAVE) FeatureBits |= KF_XSTATE;
+    if (VersionInfo.Ecx.Bits.RDRAND) FeatureBits |= KF_RDRAND;
 
     /* Check if the CPU has hyper-threading */
-    if (CpuInfo.Edx & X86_FEATURE_HT)
+    if (VersionInfo.Edx.Bits.HTT)
     {
         /* Set the number of logical CPUs */
-        Prcb->LogicalProcessorsPerPhysicalProcessor = (UCHAR)(CpuInfo.Ebx >> 16);
+        Prcb->LogicalProcessorsPerPhysicalProcessor =
+            VersionInfo.Ebx.Bits.MaximumAddressableIdsForLogicalProcessors;
         if (Prcb->LogicalProcessorsPerPhysicalProcessor > 1)
         {
             /* We're on dual-core */
@@ -207,25 +227,115 @@ KiGetFeatureBits(VOID)
         Prcb->LogicalProcessorsPerPhysicalProcessor = 1;
     }
 
-    /* Check extended cpuid features */
-    KiCpuId(&CpuInfo, 0x80000000);
-    if ((CpuInfo.Eax & 0xffffff00) == 0x80000000)
+    /* Check if CPUID_THERMAL_POWER_MANAGEMENT (0x06) is supported */
+    if (signature.MaxLeaf >= CPUID_THERMAL_POWER_MANAGEMENT)
     {
-        /* Check if CPUID 0x80000001 is supported */
-        if (CpuInfo.Eax >= 0x80000001)
+        /* Read CPUID_THERMAL_POWER_MANAGEMENT */
+        CPUID_THERMAL_POWER_MANAGEMENT_REGS PowerInfo;
+        __cpuid(PowerInfo.AsInt32, CPUID_THERMAL_POWER_MANAGEMENT);
+
+        if (PowerInfo.Undoc.Ecx.ACNT2) FeatureBits |= KF_ACNT2;
+    }
+
+    /* Check if CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (0x07) is supported */
+    if (signature.MaxLeaf >= CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS)
+    {
+        /* Read CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS */
+        CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_REGS ExtFlags;
+        __cpuidex(ExtFlags.AsInt32,
+            CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,
+            CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO);
+
+        if (ExtFlags.Ebx.Bits.SMEP) FeatureBits |= KF_SMEP;
+        if (ExtFlags.Ebx.Bits.FSGSBASE) FeatureBits |= KF_RDWRFSGSBASE;
+        if (ExtFlags.Ebx.Bits.SMAP) FeatureBits |= KF_SMAP;
+    }
+
+    /* Check if CPUID_EXTENDED_STATE (0x0D) is supported */
+    if (signature.MaxLeaf >= CPUID_EXTENDED_STATE)
+    {
+        /* Read CPUID_EXTENDED_STATE */
+        CPUID_EXTENDED_STATE_SUB_LEAF_EAX_REGS ExtStateSub;
+        __cpuidex(ExtStateSub.AsInt32,
+            CPUID_EXTENDED_STATE,
+            CPUID_EXTENDED_STATE_SUB_LEAF);
+
+        if (ExtStateSub.Eax.Bits.XSAVEOPT) FeatureBits |= KF_XSAVEOPT;
+        if (ExtStateSub.Eax.Bits.XSAVES)  FeatureBits |= KF_XSAVES;
+    }
+
+    /* Check extended cpuid features */
+    __cpuid(extendedFunction.AsInt32, CPUID_EXTENDED_FUNCTION);
+    if ((extendedFunction.MaxLeaf & 0xffffff00) == 0x80000000)
+    {
+        /* Check if CPUID_EXTENDED_CPU_SIG (0x80000001) is supported */
+        if (extendedFunction.MaxLeaf >= CPUID_EXTENDED_CPU_SIG)
         {
-            /* Check which extended features are available. */
-            KiCpuId(&CpuInfo, 0x80000001);
+            /* Read CPUID_EXTENDED_CPU_SIG */
+            CPUID_EXTENDED_CPU_SIG_REGS ExtSig;
+            __cpuid(ExtSig.AsInt32, CPUID_EXTENDED_CPU_SIG);
 
             /* Check if NX-bit is supported */
-            if (CpuInfo.Edx & X86_FEATURE_NX) FeatureBits |= KF_NX_BIT;
+            if (ExtSig.Intel.Edx.Bits.NX) FeatureBits |= KF_NX_BIT;
+            if (ExtSig.Intel.Edx.Bits.Page1GB) FeatureBits |= KF_HUGEPAGE;
+            if (ExtSig.Intel.Edx.Bits.RDTSCP) FeatureBits |= KF_RDTSCP;
 
-            /* Now handle each features for each CPU Vendor */
-            switch (Vendor)
+            /* AMD specific */
+            if (Vendor == CPU_AMD)
             {
-                case CPU_AMD:
-                    if (CpuInfo.Edx & 0x80000000) FeatureBits |= KF_3DNOW;
-                    break;
+                if (ExtSig.Amd.Edx.Bits.ThreeDNow) FeatureBits |= KF_3DNOW;
+            }
+        }
+    }
+
+    /* Vendor specific */
+    if (Vendor == CPU_INTEL)
+    {
+        FeatureBits |= KF_GENUINE_INTEL;
+
+        /* Check for models that support LBR */
+        if (VersionInfo.Eax.Bits.FamilyId == 6)
+        {
+            if ((VersionInfo.Eax.Bits.Model == 15) ||
+                (VersionInfo.Eax.Bits.Model == 22) ||
+                (VersionInfo.Eax.Bits.Model == 23) ||
+                (VersionInfo.Eax.Bits.Model == 26))
+            {
+                FeatureBits |= KF_BRANCH;
+            }
+        }
+
+        /* Check if VMX is available */
+        if (VersionInfo.Ecx.Bits.VMX)
+        {
+            /* Read PROCBASED ctls and check if secondary are allowed */
+            MSR_IA32_VMX_PROCBASED_CTLS_REGISTER ProcBasedCtls;
+            ProcBasedCtls.Uint64 = __readmsr(MSR_IA32_VMX_PROCBASED_CTLS);
+            if (ProcBasedCtls.Bits.Allowed1.ActivateSecondaryControls)
+            {
+                /* Read secondary controls and check if EPT is allowed */
+                MSR_IA32_VMX_PROCBASED_CTLS2_REGISTER ProcBasedCtls2;
+                ProcBasedCtls2.Uint64 = __readmsr(MSR_IA32_VMX_PROCBASED_CTLS2);
+                if (ProcBasedCtls2.Bits.Allowed1.EPT)
+                    FeatureBits |= KF_SLAT;
+            }
+        }
+    }
+    else if (Vendor == CPU_AMD)
+    {
+        FeatureBits |= KF_AUTHENTICAMD;
+        FeatureBits |= KF_BRANCH;
+
+        /* Check extended cpuid features */
+        if ((extendedFunction.MaxLeaf & 0xffffff00) == 0x80000000)
+        {
+            /* Check if CPUID_AMD_SVM_FEATURES (0x8000000A) is supported */
+            if (extendedFunction.MaxLeaf >= CPUID_AMD_SVM_FEATURES)
+            {
+                /* Read CPUID_AMD_SVM_FEATURES and check if Nested Paging is available */
+                CPUID_AMD_SVM_FEATURES_REGS SvmFeatures;
+                __cpuid(SvmFeatures.AsInt32, CPUID_AMD_SVM_FEATURES);
+                if (SvmFeatures.Edx.Bits.NP) FeatureBits |= KF_SLAT;
             }
         }
     }
@@ -250,7 +360,7 @@ KiReportCpuFeatures(IN PKPRCB Prcb)
     DPRINT1("Supported CPU features: ");
 
 #define print_kf_bit(kf_value) if (Prcb->FeatureBits & kf_value) DbgPrint(#kf_value " ")
-    print_kf_bit(KF_V86_VIS);
+    print_kf_bit(KF_SMEP);
     print_kf_bit(KF_RDTSC);
     print_kf_bit(KF_CR4);
     print_kf_bit(KF_CMOV);
@@ -258,25 +368,40 @@ KiReportCpuFeatures(IN PKPRCB Prcb)
     print_kf_bit(KF_LARGE_PAGE);
     print_kf_bit(KF_MTRR);
     print_kf_bit(KF_CMPXCHG8B);
-    print_kf_bit(KF_CMPXCHG16B);
     print_kf_bit(KF_MMX);
-    print_kf_bit(KF_WORKING_PTE);
+    print_kf_bit(KF_DTS);
     print_kf_bit(KF_PAT);
     print_kf_bit(KF_FXSR);
     print_kf_bit(KF_FAST_SYSCALL);
     print_kf_bit(KF_XMMI);
     print_kf_bit(KF_3DNOW);
+    print_kf_bit(KF_XSAVEOPT);
     print_kf_bit(KF_XMMI64);
-    print_kf_bit(KF_DTS);
+    print_kf_bit(KF_BRANCH);
+    print_kf_bit(KF_00040000);
+    print_kf_bit(KF_SSE3);
+    print_kf_bit(KF_CMPXCHG16B);
+    print_kf_bit(KF_AUTHENTICAMD);
+    print_kf_bit(KF_ACNT2);
+    print_kf_bit(KF_XSTATE);
+    print_kf_bit(KF_GENUINE_INTEL);
+    print_kf_bit(KF_SLAT);
+    print_kf_bit(KF_VIRT_FIRMWARE_ENABLED);
+    print_kf_bit(KF_RDWRFSGSBASE);
     print_kf_bit(KF_NX_BIT);
     print_kf_bit(KF_NX_DISABLED);
     print_kf_bit(KF_NX_ENABLED);
-    print_kf_bit(KF_SSE3);
-    //print_kf_bit(KF_SSE3SUP);
-    //print_kf_bit(KF_SSE41);
-    //print_kf_bit(KF_MONITOR);
-    //print_kf_bit(KF_POPCNT);
-    print_kf_bit(KF_XSTATE);
+    print_kf_bit(KF_RDRAND);
+    print_kf_bit(KF_SMAP);
+    print_kf_bit(KF_RDTSCP);
+    print_kf_bit(KF_HUGEPAGE);
+    print_kf_bit(KF_XSAVES);
+    print_kf_bit(KF_FPU_LEAKAGE);
+    print_kf_bit(KF_CAT);
+    print_kf_bit(KF_CET_SS);
+    print_kf_bit(KF_SSSE3);
+    print_kf_bit(KF_SSE4_1);
+    print_kf_bit(KF_SSE4_2);
 #undef print_kf_bit
 
 #define print_cf(cpu_flag) if (CpuFeatures & cpu_flag) DbgPrint(#cpu_flag " ")

ntoskrnl/ke/amd64/kiinit.c

@@ -170,7 +170,7 @@ NTAPI
 KiInitializeCpu(PKIPCR Pcr)
 {
     ULONG64 Pat;
-    ULONG FeatureBits;
+    ULONG64 FeatureBits;
 
     /* Initialize gs */
     KiInitializeSegments();
@@ -199,7 +199,8 @@ KiInitializeCpu(PKIPCR Pcr)
     FeatureBits |= KF_NX_ENABLED;
 
     /* Save feature bits */
-    Pcr->Prcb.FeatureBits = FeatureBits;
+    Pcr->Prcb.FeatureBits = (ULONG)FeatureBits;
+    Pcr->Prcb.FeatureBitsHigh = FeatureBits >> 32;
 
     /* Enable fx save restore support */
     __writecr4(__readcr4() | CR4_FXSR);
@@ -283,6 +284,8 @@ KiInitializeKernelMachineDependent(
     IN PKPRCB Prcb,
     IN PLOADER_PARAMETER_BLOCK LoaderBlock)
 {
+    ULONG64 FeatureBits;
+
     /* Set boot-level flags */
     KeI386CpuType = Prcb->CpuType;
     KeI386CpuStep = Prcb->CpuStep;
@@ -291,26 +294,52 @@ KiInitializeKernelMachineDependent(
     if (Prcb->CpuID)
         KeProcessorRevision = Prcb->CpuStep;
 
+    FeatureBits = Prcb->FeatureBits | (ULONG64)Prcb->FeatureBitsHigh << 32;
+
     /* Set basic CPU Features that user mode can read */
+    SharedUserData->ProcessorFeatures[PF_FLOATING_POINT_PRECISION_ERRATA] = FALSE;
+    SharedUserData->ProcessorFeatures[PF_FLOATING_POINT_EMULATED] = FALSE;
     SharedUserData->ProcessorFeatures[PF_COMPARE_EXCHANGE_DOUBLE] = TRUE;
-    SharedUserData->ProcessorFeatures[PF_RDTSC_INSTRUCTION_AVAILABLE] = TRUE;
-    SharedUserData->ProcessorFeatures[PF_PPC_MOVEMEM_64BIT_OK] = TRUE;
-    SharedUserData->ProcessorFeatures[PF_PAE_ENABLED] = TRUE; // ???
-    SharedUserData->ProcessorFeatures[PF_NX_ENABLED] = TRUE;
-    SharedUserData->ProcessorFeatures[PF_FASTFAIL_AVAILABLE] = TRUE;
-    SharedUserData->ProcessorFeatures[PF_XSAVE_ENABLED] = TRUE;
     SharedUserData->ProcessorFeatures[PF_MMX_INSTRUCTIONS_AVAILABLE] =
-        (Prcb->FeatureBits & KF_MMX) ? TRUE: FALSE;
+        (FeatureBits & KF_MMX) ? TRUE : FALSE;
     SharedUserData->ProcessorFeatures[PF_XMMI_INSTRUCTIONS_AVAILABLE] =
-        ((Prcb->FeatureBits & KF_FXSR) && (Prcb->FeatureBits & KF_XMMI)) ? TRUE: FALSE;
-    SharedUserData->ProcessorFeatures[PF_XMMI64_INSTRUCTIONS_AVAILABLE] =
-        ((Prcb->FeatureBits & KF_FXSR) && (Prcb->FeatureBits & KF_XMMI64)) ? TRUE: FALSE;
+        ((FeatureBits & KF_FXSR) && (FeatureBits & KF_XMMI)) ? TRUE : FALSE;
     SharedUserData->ProcessorFeatures[PF_3DNOW_INSTRUCTIONS_AVAILABLE] =
-        (Prcb->FeatureBits & KF_3DNOW) ? TRUE: FALSE;
+        (FeatureBits & KF_3DNOW) ? TRUE : FALSE;
+    SharedUserData->ProcessorFeatures[PF_RDTSC_INSTRUCTION_AVAILABLE] = TRUE;
+    SharedUserData->ProcessorFeatures[PF_PAE_ENABLED] = TRUE; // ???
+    SharedUserData->ProcessorFeatures[PF_XMMI64_INSTRUCTIONS_AVAILABLE] =
+        ((FeatureBits & KF_FXSR) && (FeatureBits & KF_XMMI64)) ? TRUE : FALSE;
+    SharedUserData->ProcessorFeatures[PF_SSE_DAZ_MODE_AVAILABLE] = FALSE; // ???
+    SharedUserData->ProcessorFeatures[PF_NX_ENABLED] = TRUE;
     SharedUserData->ProcessorFeatures[PF_SSE3_INSTRUCTIONS_AVAILABLE] =
-        (Prcb->FeatureBits & KF_SSE3) ? TRUE: FALSE;
+        (FeatureBits & KF_SSE3) ? TRUE : FALSE;
     SharedUserData->ProcessorFeatures[PF_COMPARE_EXCHANGE128] =
-        (Prcb->FeatureBits & KF_CMPXCHG16B) ? TRUE: FALSE;
+        (FeatureBits & KF_CMPXCHG16B) ? TRUE : FALSE;
+    SharedUserData->ProcessorFeatures[PF_COMPARE64_EXCHANGE128] = FALSE; // ???
+    SharedUserData->ProcessorFeatures[PF_CHANNELS_ENABLED] = FALSE; // ???
+    SharedUserData->ProcessorFeatures[PF_XSAVE_ENABLED] = FALSE; // FIXME
+    SharedUserData->ProcessorFeatures[PF_SECOND_LEVEL_ADDRESS_TRANSLATION] =
+        (FeatureBits & KF_SLAT) ? TRUE : FALSE;
+    SharedUserData->ProcessorFeatures[PF_VIRT_FIRMWARE_ENABLED] =
+        (FeatureBits & KF_VIRT_FIRMWARE_ENABLED) ? TRUE : FALSE;
+    SharedUserData->ProcessorFeatures[PF_RDWRFSGSBASE_AVAILABLE] =
+        (FeatureBits & KF_RDWRFSGSBASE) ? TRUE : FALSE;
+    SharedUserData->ProcessorFeatures[PF_FASTFAIL_AVAILABLE] = TRUE;
+    SharedUserData->ProcessorFeatures[PF_RDRAND_INSTRUCTION_AVAILABLE] =
+        (FeatureBits & KF_RDRAND) ? TRUE : FALSE;
+    SharedUserData->ProcessorFeatures[PF_RDTSCP_INSTRUCTION_AVAILABLE] =
+        (FeatureBits & KF_RDTSCP) ? TRUE : FALSE;
+    SharedUserData->ProcessorFeatures[PF_RDPID_INSTRUCTION_AVAILABLE] = FALSE; // ???
+    SharedUserData->ProcessorFeatures[PF_SSSE3_INSTRUCTIONS_AVAILABLE] =
+        (FeatureBits & KF_SSSE3) ? TRUE : FALSE;
+    SharedUserData->ProcessorFeatures[PF_SSE4_1_INSTRUCTIONS_AVAILABLE] =
+        (FeatureBits & KF_SSE4_1) ? TRUE : FALSE;
+    SharedUserData->ProcessorFeatures[PF_SSE4_2_INSTRUCTIONS_AVAILABLE] =
+        (FeatureBits & KF_SSE4_2) ? TRUE : FALSE;
+    SharedUserData->ProcessorFeatures[PF_AVX_INSTRUCTIONS_AVAILABLE] = FALSE; // FIXME
+    SharedUserData->ProcessorFeatures[PF_AVX2_INSTRUCTIONS_AVAILABLE] = FALSE; // FIXME
+    SharedUserData->ProcessorFeatures[PF_AVX512F_INSTRUCTIONS_AVAILABLE] = FALSE; // FIXME
 
     /* Set the default NX policy (opt-in) */
     SharedUserData->NXSupportPolicy = NX_SUPPORT_POLICY_OPTIN;

sdk/include/ndk/amd64/ketypes.h

@@ -24,6 +24,62 @@ Author:
 // Dependencies
 //
 
+//
+// Kernel Feature Bits
+// See https://www.geoffchappell.com/studies/windows/km/ntoskrnl/structs/kprcb/featurebits.htm?tx=61&ts=0,1400
+//
+#define KF_SMEP                         0x00000001 // Win 6.2
+#define KF_RDTSC                        0x00000002 // From ks386.inc, ksamd64.inc
+#define KF_CR4                          0x00000004 // From ks386.inc, ksamd64.inc
+#define KF_CMOV                         0x00000008
+#define KF_GLOBAL_PAGE                  0x00000010 // From ks386.inc, ksamd64.inc
+#define KF_LARGE_PAGE                   0x00000020 // From ks386.inc, ksamd64.inc
+#define KF_MTRR                         0x00000040
+#define KF_CMPXCHG8B                    0x00000080 // From ks386.inc, ksamd64.inc
+#define KF_MMX                          0x00000100
+#define KF_DTS                          0x00000200 // Win 5.2-6.2
+#define KF_PAT                          0x00000400
+#define KF_FXSR                         0x00000800
+#define KF_FAST_SYSCALL                 0x00001000 // From ks386.inc, ksamd64.inc
+#define KF_XMMI                         0x00002000 // SSE
+#define KF_3DNOW                        0x00004000
+#define KF_AMDK6MTRR                    0x00008000 // Win 5.0-6.1
+#define KF_XSAVEOPT                     0x00008000 // From KF_XSAVEOPT_BIT
+#define KF_XMMI64                       0x00010000 // SSE2
+#define KF_BRANCH                       0x00020000 // From ksamd64.inc, Win 6.1-6.2 
+#define KF_00040000                     0x00040000 // Unclear
+#define KF_SSE3                         0x00080000 // Win 6.0+
+#define KF_CMPXCHG16B                   0x00100000 // Win 6.0-6.2
+#define KF_AUTHENTICAMD                 0x00200000 // Win 6.1+
+#define KF_ACNT2                        0x00400000 // Win 6.1+
+#define KF_XSTATE                       0x00800000 // From ksamd64.inc, Win 6.1+
+#define KF_GENUINE_INTEL                0x01000000 // Win 6.1+
+#define KF_02000000                     0x02000000 // Unclear
+#define KF_SLAT                         0x04000000 // Win 6.2+, Intel: EPT supported
+#define KF_VIRT_FIRMWARE_ENABLED        0x08000000 // Win 6.2+
+#define KF_RDWRFSGSBASE                 0x10000000 // From ksamd64.inc KF_RDWRFSGSBASE_BIT (0x1C)
+#define KF_NX_BIT                       0x20000000
+#define KF_NX_DISABLED                  0x40000000
+#define KF_NX_ENABLED                   0x80000000
+#define KF_RDRAND               0x0000000100000000ULL // Win 10.0+
+#define KF_SMAP                 0x0000000200000000ULL // From ksamd64.inc
+#define KF_RDTSCP               0x0000000400000000ULL // Win 10.0+
+#define KF_HUGEPAGE             0x0000002000000000ULL // Win 10.0 1607+
+#define KF_XSAVES               0x0000004000000000ULL // From ksamd64.inc KF_XSAVES_BIT (0x26)
+#define KF_FPU_LEAKAGE          0x0000020000000000ULL // From ksamd64.inc KF_FPU_LEAKAGE_BIT (0x29)
+#define KF_CAT                  0x0000100000000000ULL // From ksamd64.inc KF_CAT_BIT (0x02C)
+#define KF_CET_SS               0x0000400000000000ULL // From ksamd64.inc
+#define KF_SSSE3                0x0000800000000000ULL
+#define KF_SSE4_1               0x0001000000000000ULL
+#define KF_SSE4_2               0x0002000000000000ULL
+
+#define KF_XSAVEOPT_BIT                 15 // From ksamd64.inc (0x0F -> 0x8000)
+#define KF_XSTATE_BIT                   23 // From ksamd64.inc (0x17 -> 0x800000)
+#define KF_RDWRFSGSBASE_BIT             28 // From ksamd64.inc (0x1C -> 0x10000000)
+#define KF_XSAVES_BIT                   38 // From ksamd64.inc (0x26 -> 0x4000000000)
+#define KF_FPU_LEAKAGE_BIT              41 // From ksamd64.inc (0x29 -> 0x20000000000)
+#define KF_CAT_BIT                      44 // From ksamd64.inc (0x2C -> 0x100000000000)
+
 //
 // KPCR Access for non-IA64 builds
 //
@@ -193,7 +249,7 @@ typedef enum
 #define MSR_GS_SWAP             0xC0000102
 #define MSR_MCG_STATUS          0x017A
 #define MSR_AMD_ACCESS          0x9C5A203A
-#define MSR_IA32_MISC_ENABLE    0x01A0
+#define MSR_IA32_MISC_ENABLE    0x000001A0
 #define MSR_LAST_BRANCH_FROM    0x01DB
 #define MSR_LAST_BRANCH_TO      0x01DC
 #define MSR_LAST_EXCEPTION_FROM 0x01DD
@@ -854,6 +910,9 @@ typedef struct _KPRCB
     CACHE_DESCRIPTOR Cache[5];
     ULONG CacheCount;
 #endif
+#ifdef __REACTOS__
+    ULONG FeatureBitsHigh;
+#endif
 } KPRCB, *PKPRCB;
 
 //

sdk/include/ndk/i386/ketypes.h

@@ -23,6 +23,52 @@ Author:
 // Dependencies
 //
 
+//
+// Kernel Feature Bits
+// See https://www.geoffchappell.com/studies/windows/km/ntoskrnl/structs/kprcb/featurebits.htm?tx=61&ts=0,1400
+//
+#define KF_V86_VIS                      0x00000001 // From ks386.inc
+#define KF_RDTSC                        0x00000002 // From ks386.inc, ksamd64.inc
+#define KF_CR4                          0x00000004 // From ks386.inc, ksamd64.inc
+#define KF_CMOV                         0x00000008
+#define KF_GLOBAL_PAGE                  0x00000010 // From ks386.inc, ksamd64.inc
+#define KF_LARGE_PAGE                   0x00000020 // From ks386.inc, ksamd64.inc
+#define KF_MTRR                         0x00000040
+#define KF_CMPXCHG8B                    0x00000080 // From ks386.inc, ksamd64.inc
+#define KF_MMX                          0x00000100
+#define KF_WORKING_PTE                  0x00000200
+#define KF_PAT                          0x00000400
+#define KF_FXSR                         0x00000800
+#define KF_FAST_SYSCALL                 0x00001000 // From ks386.inc, ksamd64.inc
+#define KF_XMMI                         0x00002000 // SSE
+#define KF_3DNOW                        0x00004000
+#define KF_AMDK6MTRR                    0x00008000 // Win 5.0-6.1
+#define KF_XSAVEOPT                     0x00008000 // From KF_XSAVEOPT_BIT
+#define KF_XMMI64                       0x00010000 // SSE2
+#define KF_DTS                          0x00020000
+#define KF_CLFLUSH                      0x00040000 // Win 6.0+
+#define KF_SSE3                         0x00080000 // Win 6.0+
+#define KF_AUTHENTICAMD                 0x00100000 // Win 6.1+ (family 5+)
+#define KF_ACNT2                        0x00200000 // Win 6.1+
+#define KF_XSTATE                       0x00400000 // From ks386.inc, Win 6.1+
+#define KF_GENUINE_INTEL                0x00800000 // Win 6.1+
+#define KF_SMEP                         0x01000000 // Win 6.2+
+#define KF_RDRAND                       0x02000000 // Win 6.3+
+#define KF_SLAT                         0x04000000 // Win 6.2+, Intel: EPT supported
+#define KF_08000000                     0x08000000 // Win 6.2+
+#define KF_NX_BIT                       0x20000000
+#define KF_NX_DISABLED                  0x40000000
+#define KF_NX_ENABLED                   0x80000000
+#define KF_RDTSCP               0x0000000100000000ULL // Win 10.0+
+#define KF_CLFLUSHOPT           0x0000000200000000ULL // Win 10.0+
+#define KF_HDC                  0x0000000400000000ULL // Win 10.0+
+#define KF_FPU_LEAKAGE          0x0000001000000000ULL // From ks386.inc KF_FPU_LEAKAGE_BIT
+#define KF_SSSE3                0x0000004000000000ULL
+#define KF_SSE4_1               0x0000008000000000ULL
+#define KF_SSE4_2               0x0000010000000000ULL
+
+#define KF_FPU_LEAKAGE_BIT              36 // From ks386.inc (0x24 -> 0x1000000000)
+
 //
 // KPCR Access for non-IA64 builds
 //

sdk/include/ndk/ketypes.h

@@ -137,39 +137,6 @@ Author:
 #define WAIT_QUANTUM_DECREMENT          1
 #define CLOCK_QUANTUM_DECREMENT         3
 
-//
-// Kernel Feature Bits
-//
-#define KF_V86_VIS                      0x00000001
-#define KF_RDTSC                        0x00000002
-#define KF_CR4                          0x00000004
-#define KF_CMOV                         0x00000008
-#define KF_GLOBAL_PAGE                  0x00000010
-#define KF_LARGE_PAGE                   0x00000020
-#define KF_MTRR                         0x00000040
-#define KF_CMPXCHG8B                    0x00000080
-#define KF_MMX                          0x00000100
-#define KF_WORKING_PTE                  0x00000200
-#define KF_PAT                          0x00000400
-#define KF_FXSR                         0x00000800
-#define KF_FAST_SYSCALL                 0x00001000
-#define KF_XMMI                         0x00002000
-#define KF_3DNOW                        0x00004000
-#define KF_AMDK6MTRR                    0x00008000
-#define KF_XMMI64                       0x00010000
-#define KF_DTS                          0x00020000
-#define KF_BRANCH                       0x00020000 // from ksamd64.inc
-#define KF_SSE3                         0x00080000
-#define KF_CMPXCHG16B                   0x00100000
-#define KF_XSTATE                       0x00800000 // from ks386.inc, ksamd64.inc
-#define KF_NX_BIT                       0x20000000
-#define KF_NX_DISABLED                  0x40000000
-#define KF_NX_ENABLED                   0x80000000
-
-#define KF_XSAVEOPT_BIT                 15
-#define KF_XSTATE_BIT                   23
-#define KF_RDWRFSGSBASE_BIT             28
-
 //
 // Internal Exception Codes
 //

sdk/include/reactos/x86x64/Amd/Cpuid.h

@@ -0,0 +1,733 @@
+/** @file
+  CPUID leaf definitions.
+
+  Provides defines for CPUID leaf indexes.  Data structures are provided for
+  registers returned by a CPUID leaf that contain one or more bit fields.
+  If a register returned is a single 32-bit value, then a data structure is
+  not provided for that register.
+
+  Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>
+
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+
+  @par Specification Reference:
+  AMD64 Architecture Programming Manual volume 2, March 2017, Sections 15.34
+
+**/
+
+#ifndef __AMD_CPUID_H__
+#define __AMD_CPUID_H__
+
+/**
+CPUID Signature Information
+
+@param   EAX  CPUID_SIGNATURE (0x00)
+
+@retval  EAX  Returns the highest value the CPUID instruction recognizes for
+              returning basic processor information. The value is returned is
+              processor specific.
+@retval  EBX  First 4 characters of a vendor identification string.
+@retval  ECX  Last 4 characters of a vendor identification string.
+@retval  EDX  Middle 4 characters of a vendor identification string.
+
+**/
+
+///
+/// @{ CPUID signature values returned by AMD processors
+///
+#define CPUID_SIGNATURE_AUTHENTIC_AMD_EBX  SIGNATURE_32 ('A', 'u', 't', 'h')
+#define CPUID_SIGNATURE_AUTHENTIC_AMD_EDX  SIGNATURE_32 ('e', 'n', 't', 'i')
+#define CPUID_SIGNATURE_AUTHENTIC_AMD_ECX  SIGNATURE_32 ('c', 'A', 'M', 'D')
+///
+/// @}
+///
+
+/**
+  CPUID Extended Processor Signature and Features
+
+  @param   EAX  CPUID_EXTENDED_CPU_SIG (0x80000001)
+
+  @retval  EAX  Extended Family, Model, Stepping Identifiers
+                described by the type CPUID_AMD_EXTENDED_CPU_SIG_EAX.
+  @retval  EBX  Brand Identifier
+                described by the type CPUID_AMD_EXTENDED_CPU_SIG_EBX.
+  @retval  ECX  Extended Feature Identifiers
+                described by the type CPUID_AMD_EXTENDED_CPU_SIG_ECX.
+  @retval  EDX  Extended Feature Identifiers
+                described by the type CPUID_AMD_EXTENDED_CPU_SIG_EDX.
+**/
+
+/**
+  CPUID Extended Processor Signature and Features EAX for CPUID leaf
+  #CPUID_EXTENDED_CPU_SIG.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 3:0] Stepping.
+    ///
+    UINT32    Stepping   : 4;
+    ///
+    /// [Bits 7:4] Base Model.
+    ///
+    UINT32    BaseModel  : 4;
+    ///
+    /// [Bits 11:8] Base Family.
+    ///
+    UINT32    BaseFamily : 4;
+    ///
+    /// [Bit 15:12] Reserved.
+    ///
+    UINT32    Reserved1  : 4;
+    ///
+    /// [Bits 19:16] Extended Model.
+    ///
+    UINT32    ExtModel   : 4;
+    ///
+    /// [Bits 27:20] Extended Family.
+    ///
+    UINT32    ExtFamily  : 8;
+    ///
+    /// [Bit 31:28] Reserved.
+    ///
+    UINT32    Reserved2  : 4;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32    Uint32;
+} CPUID_AMD_EXTENDED_CPU_SIG_EAX;
+
+/**
+  CPUID Extended Processor Signature and Features EBX for CPUID leaf
+  #CPUID_EXTENDED_CPU_SIG.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 27:0] Reserved.
+    ///
+    UINT32    Reserved : 28;
+    ///
+    /// [Bit 31:28] Package Type.
+    ///
+    UINT32    PkgType  : 4;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32    Uint32;
+} CPUID_AMD_EXTENDED_CPU_SIG_EBX;
+
+/**
+  CPUID Extended Processor Signature and Features ECX for CPUID leaf
+  #CPUID_EXTENDED_CPU_SIG.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] LAHF/SAHF available in 64-bit mode.
+    ///
+    UINT32    LAHF_SAHF               : 1;
+    ///
+    /// [Bit 1] Core multi-processing legacy mode.
+    ///
+    UINT32    CmpLegacy               : 1;
+    ///
+    /// [Bit 2] Secure Virtual Mode feature.
+    ///
+    UINT32    SVM                     : 1;
+    ///
+    /// [Bit 3] Extended APIC register space.
+    ///
+    UINT32    ExtApicSpace            : 1;
+    ///
+    /// [Bit 4] LOCK MOV CR0 means MOV CR8.
+    ///
+    UINT32    AltMovCr8               : 1;
+    ///
+    /// [Bit 5] LZCNT instruction support.
+    ///
+    UINT32    LZCNT                   : 1;
+    ///
+    /// [Bit 6] SSE4A instruction support.
+    ///
+    UINT32    SSE4A                   : 1;
+    ///
+    /// [Bit 7] Misaligned SSE Mode.
+    ///
+    UINT32    MisAlignSse             : 1;
+    ///
+    /// [Bit 8] ThreeDNow Prefetch instructions.
+    ///
+    UINT32    PREFETCHW               : 1;
+    ///
+    /// [Bit 9] OS Visible Work-around support.
+    ///
+    UINT32    OSVW                    : 1;
+    ///
+    /// [Bit 10] Instruction Based Sampling.
+    ///
+    UINT32    IBS                     : 1;
+    ///
+    /// [Bit 11] Extended Operation Support.
+    ///
+    UINT32    XOP                     : 1;
+    ///
+    /// [Bit 12] SKINIT and STGI support.
+    ///
+    UINT32    SKINIT                  : 1;
+    ///
+    /// [Bit 13] Watchdog Timer support.
+    ///
+    UINT32    WDT                     : 1;
+    ///
+    /// [Bit 14] Reserved.
+    ///
+    UINT32    Reserved1               : 1;
+    ///
+    /// [Bit 15] Lightweight Profiling support.
+    ///
+    UINT32    LWP                     : 1;
+    ///
+    /// [Bit 16] 4-Operand FMA instruction support.
+    ///
+    UINT32    FMA4                    : 1;
+    ///
+    /// [Bit 17] Translation Cache Extension.
+    ///
+    UINT32    TCE                     : 1;
+    ///
+    /// [Bit 21:18] Reserved.
+    ///
+    UINT32    Reserved2               : 4;
+    ///
+    /// [Bit 22] Topology Extensions support.
+    ///
+    UINT32    TopologyExtensions      : 1;
+    ///
+    /// [Bit 23] Core Performance Counter Extensions.
+    ///
+    UINT32    PerfCtrExtCore          : 1;
+    ///
+    /// [Bit 25:24] Reserved.
+    ///
+    UINT32    Reserved3               : 2;
+    ///
+    /// [Bit 26] Data Breakpoint Extension.
+    ///
+    UINT32    DataBreakpointExtension : 1;
+    ///
+    /// [Bit 27] Performance Time-Stamp Counter.
+    ///
+    UINT32    PerfTsc                 : 1;
+    ///
+    /// [Bit 28] L3 Performance Counter Extensions.
+    ///
+    UINT32    PerfCtrExtL3            : 1;
+    ///
+    /// [Bit 29] MWAITX and MONITORX capability.
+    ///
+    UINT32    MwaitExtended           : 1;
+    ///
+    /// [Bit 31:30] Reserved.
+    ///
+    UINT32    Reserved4               : 2;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32    Uint32;
+} CPUID_AMD_EXTENDED_CPU_SIG_ECX;
+
+/**
+  CPUID Extended Processor Signature and Features EDX for CPUID leaf
+  #CPUID_EXTENDED_CPU_SIG.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] x87 floating point unit on-chip.
+    ///
+    UINT32    FPU            : 1;
+    ///
+    /// [Bit 1] Virtual-mode enhancements.
+    ///
+    UINT32    VME            : 1;
+    ///
+    /// [Bit 2] Debugging extensions, IO breakpoints, CR4.DE.
+    ///
+    UINT32    DE             : 1;
+    ///
+    /// [Bit 3] Page-size extensions (4 MB pages).
+    ///
+    UINT32    PSE            : 1;
+    ///
+    /// [Bit 4] Time stamp counter, RDTSC/RDTSCP instructions, CR4.TSD.
+    ///
+    UINT32    TSC            : 1;
+    ///
+    /// [Bit 5] MSRs, with RDMSR and WRMSR instructions.
+    ///
+    UINT32    MSR            : 1;
+    ///
+    /// [Bit 6] Physical-address extensions (PAE).
+    ///
+    UINT32    PAE            : 1;
+    ///
+    /// [Bit 7] Machine check exception, CR4.MCE.
+    ///
+    UINT32    MCE            : 1;
+    ///
+    /// [Bit 8] CMPXCHG8B instruction.
+    ///
+    UINT32    CMPXCHG8B      : 1;
+    ///
+    /// [Bit 9] APIC exists and is enabled.
+    ///
+    UINT32    APIC           : 1;
+    ///
+    /// [Bit 10] Reserved.
+    ///
+    UINT32    Reserved1      : 1;
+    ///
+    /// [Bit 11] SYSCALL and SYSRET instructions.
+    ///
+    UINT32    SYSCALL_SYSRET : 1;
+    ///
+    /// [Bit 12] Memory-type range registers.
+    ///
+    UINT32    MTRR           : 1;
+    ///
+    /// [Bit 13] Page global extension, CR4.PGE.
+    ///
+    UINT32    PGE            : 1;
+    ///
+    /// [Bit 14] Machine check architecture, MCG_CAP.
+    ///
+    UINT32    MCA            : 1;
+    ///
+    /// [Bit 15] Conditional move instructions, CMOV, FCOMI, FCMOV.
+    ///
+    UINT32    CMOV           : 1;
+    ///
+    /// [Bit 16] Page attribute table.
+    ///
+    UINT32    PAT            : 1;
+    ///
+    /// [Bit 17] Page-size extensions.
+    ///
+    UINT32    PSE36          : 1;
+    ///
+    /// [Bit 19:18] Reserved.
+    ///
+    UINT32    Reserved2      : 2;
+    ///
+    /// [Bit 20] No-execute page protection.
+    ///
+    UINT32    NX             : 1;
+    ///
+    /// [Bit 21] Reserved.
+    ///
+    UINT32    Reserved3      : 1;
+    ///
+    /// [Bit 22] AMD Extensions to MMX instructions.
+    ///
+    UINT32    MmxExt         : 1;
+    ///
+    /// [Bit 23] MMX instructions.
+    ///
+    UINT32    MMX            : 1;
+    ///
+    /// [Bit 24] FXSAVE and FXRSTOR instructions.
+    ///
+    UINT32    FFSR           : 1;
+    ///
+    /// [Bit 25] FXSAVE and FXRSTOR instruction optimizations.
+    ///
+    UINT32    FFXSR          : 1;
+    ///
+    /// [Bit 26] 1-GByte large page support.
+    ///
+    UINT32    Page1GB        : 1;
+    ///
+    /// [Bit 27] RDTSCP instructions.
+    ///
+    UINT32    RDTSCP         : 1;
+    ///
+    /// [Bit 28] Reserved.
+    ///
+    UINT32    Reserved4      : 1;
+    ///
+    /// [Bit 29] Long Mode.
+    ///
+    UINT32    LM             : 1;
+    ///
+    /// [Bit 30] 3DNow! instructions.
+    ///
+    UINT32    ThreeDNow      : 1;
+    ///
+    /// [Bit 31] AMD Extensions to 3DNow! instructions.
+    ///
+    UINT32    ThreeDNowExt   : 1;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32    Uint32;
+} CPUID_AMD_EXTENDED_CPU_SIG_EDX;
+
+/**
+CPUID Linear Physical Address Size
+
+@param   EAX  CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008)
+
+@retval  EAX  Linear/Physical Address Size described by the type
+              CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX.
+@retval  EBX  Linear/Physical Address Size described by the type
+              CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX.
+@retval  ECX  Linear/Physical Address Size described by the type
+              CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX.
+@retval  EDX  Reserved.
+**/
+
+/**
+  CPUID Linear Physical Address Size EAX for CPUID leaf
+  #CPUID_VIR_PHY_ADDRESS_SIZE.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Maximum physical byte address size in bits.
+    ///
+    UINT32    PhysicalAddressBits : 8;
+    ///
+    /// [Bits 15:8] Maximum linear byte address size in bits.
+    ///
+    UINT32    LinearAddressBits   : 8;
+    ///
+    /// [Bits 23:16] Maximum guest physical byte address size in bits.
+    ///
+    UINT32    GuestPhysAddrSize   : 8;
+    ///
+    /// [Bit 31:24] Reserved.
+    ///
+    UINT32    Reserved            : 8;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32    Uint32;
+} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX;
+
+/**
+  CPUID Linear Physical Address Size EBX for CPUID leaf
+  #CPUID_VIR_PHY_ADDRESS_SIZE.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 0] Clear Zero Instruction.
+    ///
+    UINT32    CLZERO     : 1;
+    ///
+    /// [Bits 1] Instructions retired count support.
+    ///
+    UINT32    IRPerf     : 1;
+    ///
+    /// [Bits 2] Restore error pointers for XSave instructions.
+    ///
+    UINT32    XSaveErPtr : 1;
+    ///
+    /// [Bit 31:3] Reserved.
+    ///
+    UINT32    Reserved   : 29;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32    Uint32;
+} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX;
+
+/**
+  CPUID Linear Physical Address Size ECX for CPUID leaf
+  #CPUID_VIR_PHY_ADDRESS_SIZE.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Number of threads - 1.
+    ///
+    UINT32    NC               : 8;
+    ///
+    /// [Bit 11:8] Reserved.
+    ///
+    UINT32    Reserved1        : 4;
+    ///
+    /// [Bits 15:12] APIC ID size.
+    ///
+    UINT32    ApicIdCoreIdSize : 4;
+    ///
+    /// [Bits 17:16] Performance time-stamp counter size.
+    ///
+    UINT32    PerfTscSize      : 2;
+    ///
+    /// [Bit 31:18] Reserved.
+    ///
+    UINT32    Reserved2        : 14;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32    Uint32;
+} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX;
+
+/**
+  CPUID AMD Processor Topology
+
+  @param   EAX  CPUID_AMD_PROCESSOR_TOPOLOGY (0x8000001E)
+
+  @retval  EAX  Extended APIC ID described by the type
+                CPUID_AMD_PROCESSOR_TOPOLOGY_EAX.
+  @retval  EBX  Core Identifiers described by the type
+                CPUID_AMD_PROCESSOR_TOPOLOGY_EBX.
+  @retval  ECX  Node Identifiers described by the type
+                CPUID_AMD_PROCESSOR_TOPOLOGY_ECX.
+  @retval  EDX  Reserved.
+**/
+#define CPUID_AMD_PROCESSOR_TOPOLOGY  0x8000001E
+
+/**
+  CPUID AMD Processor Topology EAX for CPUID leaf
+  #CPUID_AMD_PROCESSOR_TOPOLOGY.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 31:0] Extended APIC Id.
+    ///
+    UINT32    ExtendedApicId;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32    Uint32;
+} CPUID_AMD_PROCESSOR_TOPOLOGY_EAX;
+
+/**
+  CPUID AMD Processor Topology EBX for CPUID leaf
+  #CPUID_AMD_PROCESSOR_TOPOLOGY.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Core Id.
+    ///
+    UINT32    CoreId         : 8;
+    ///
+    /// [Bits 15:8] Threads per core.
+    ///
+    UINT32    ThreadsPerCore : 8;
+    ///
+    /// [Bit 31:16] Reserved.
+    ///
+    UINT32    Reserved       : 16;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32    Uint32;
+} CPUID_AMD_PROCESSOR_TOPOLOGY_EBX;
+
+/**
+  CPUID AMD Processor Topology ECX for CPUID leaf
+  #CPUID_AMD_PROCESSOR_TOPOLOGY.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bits 7:0] Node Id.
+    ///
+    UINT32    NodeId            : 8;
+    ///
+    /// [Bits 10:8] Nodes per processor.
+    ///
+    UINT32    NodesPerProcessor : 3;
+    ///
+    /// [Bit 31:11] Reserved.
+    ///
+    UINT32    Reserved          : 21;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32    Uint32;
+} CPUID_AMD_PROCESSOR_TOPOLOGY_ECX;
+
+/**
+  CPUID Memory Encryption Information
+
+  @param   EAX  CPUID_MEMORY_ENCRYPTION_INFO (0x8000001F)
+
+  @retval  EAX  Returns the memory encryption feature support status.
+  @retval  EBX  If memory encryption feature is present then return
+                the page table bit number used to enable memory encryption support
+                and reducing of physical address space in bits.
+  @retval  ECX  Returns number of encrypted guest supported simultaneously.
+  @retval  EDX  Returns minimum SEV enabled and SEV disabled ASID.
+
+  <b>Example usage</b>
+  @code
+  UINT32 Eax;
+  UINT32 Ebx;
+  UINT32 Ecx;
+  UINT32 Edx;
+
+  AsmCpuid (CPUID_MEMORY_ENCRYPTION_INFO, &Eax, &Ebx, &Ecx, &Edx);
+  @endcode
+**/
+
+#define CPUID_MEMORY_ENCRYPTION_INFO  0x8000001F
+
+/**
+  CPUID Memory Encryption support information EAX for CPUID leaf
+  #CPUID_MEMORY_ENCRYPTION_INFO.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 0] Secure Memory Encryption (Sme) Support
+    ///
+    UINT32    SmeBit          : 1;
+
+    ///
+    /// [Bit 1] Secure Encrypted Virtualization (Sev) Support
+    ///
+    UINT32    SevBit          : 1;
+
+    ///
+    /// [Bit 2] Page flush MSR support
+    ///
+    UINT32    PageFlushMsrBit : 1;
+
+    ///
+    /// [Bit 3] Encrypted state support
+    ///
+    UINT32    SevEsBit        : 1;
+
+    ///
+    /// [Bit 31:4] Reserved
+    ///
+    UINT32    ReservedBits    : 28;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32    Uint32;
+} CPUID_MEMORY_ENCRYPTION_INFO_EAX;
+
+/**
+  CPUID Memory Encryption support information EBX for CPUID leaf
+  #CPUID_MEMORY_ENCRYPTION_INFO.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 5:0] Page table bit number used to enable memory encryption
+    ///
+    UINT32    PtePosBits      : 6;
+
+    ///
+    /// [Bit 11:6] Reduction of system physical address space bits when
+    ///  memory encryption is enabled
+    ///
+    UINT32    ReducedPhysBits : 5;
+
+    ///
+    /// [Bit 31:12] Reserved
+    ///
+    UINT32    ReservedBits    : 21;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32    Uint32;
+} CPUID_MEMORY_ENCRYPTION_INFO_EBX;
+
+/**
+  CPUID Memory Encryption support information ECX for CPUID leaf
+  #CPUID_MEMORY_ENCRYPTION_INFO.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 31:0] Number of encrypted guest supported simultaneously
+    ///
+    UINT32    NumGuests;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32    Uint32;
+} CPUID_MEMORY_ENCRYPTION_INFO_ECX;
+
+/**
+  CPUID Memory Encryption support information EDX for CPUID leaf
+  #CPUID_MEMORY_ENCRYPTION_INFO.
+**/
+typedef union {
+  ///
+  /// Individual bit fields
+  ///
+  struct {
+    ///
+    /// [Bit 31:0] Minimum SEV enabled, SEV-ES disabled ASID
+    ///
+    UINT32    MinAsid;
+  } Bits;
+  ///
+  /// All bit fields as a 32-bit value
+  ///
+  UINT32    Uint32;
+} CPUID_MEMORY_ENCRYPTION_INFO_EDX;
+
+#endif

sdk/include/reactos/x86x64/Cpuid.h

@@ -0,0 +1,208 @@
+/*
+ * PROJECT:     ReactOS SDK
+ * LICENSE:     MIT (https://spdx.org/licenses/MIT)
+ * PURPOSE:     Provides CPUID structure definitions
+ * COPYRIGHT:   Copyright 2023 Timo Kreuzer <timo.kreuzer@reactos.org>
+ */
+
+#define CHAR8 char
+
+#include "Intel/Cpuid.h"
+#include "Amd/Cpuid.h"
+
+// CPUID_SIGNATURE (0)
+typedef union
+{
+    INT32 AsInt32[4];
+    struct
+    {
+        UINT32 MaxLeaf;
+        CHAR SignatureScrambled[12];
+    };
+} CPUID_SIGNATURE_REGS;
+
+// CPUID_VERSION_INFO (1)
+typedef union
+{
+    INT32 AsInt32[4];
+    struct
+    {
+        CPUID_VERSION_INFO_EAX Eax;
+        CPUID_VERSION_INFO_EBX Ebx;
+        CPUID_VERSION_INFO_ECX Ecx;
+        CPUID_VERSION_INFO_EDX Edx;
+    };
+} CPUID_VERSION_INFO_REGS;
+
+// CPUID_EXTENDED_FUNCTION (0x80000000)
+typedef union
+{
+    INT32 AsInt32[4];
+    struct
+    {
+        UINT32 MaxLeaf;
+        UINT32 ReservedEbx;
+        UINT32 ReservedEcx;
+        UINT32 ReservedEdx;
+    };
+} CPUID_EXTENDED_FUNCTION_REGS;
+
+// CPUID_THERMAL_POWER_MANAGEMENT (6)
+typedef union
+{
+    INT32 AsInt32[4];
+    struct
+    {
+        CPUID_THERMAL_POWER_MANAGEMENT_EAX Eax;
+        CPUID_THERMAL_POWER_MANAGEMENT_EBX Ebx;
+        CPUID_THERMAL_POWER_MANAGEMENT_ECX Ecx;
+        UINT32 ReservedEdx;
+    };
+    struct
+    {
+        UINT32 Eax;
+        UINT32 Ebx;
+        struct
+        {
+            UINT32 HardwareCoordinationFeedback : 1;
+            UINT32 ACNT2 : 1; // See https://en.wikipedia.org/wiki/CPUID
+        } Ecx;
+    } Undoc;
+} CPUID_THERMAL_POWER_MANAGEMENT_REGS;
+
+// CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (0x07)
+typedef union
+{
+    INT32 AsInt32[4];
+    struct
+    {
+        UINT32 Eax;
+        CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;
+        CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX Ecx;
+        CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EDX Edx;
+    };
+} CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_REGS;
+
+// CPUID_EXTENDED_STATE (0x0D)
+// CPUID_EXTENDED_STATE_MAIN_LEAF (0x00)
+typedef union
+{
+    INT32 AsInt32[4];
+    struct
+    {
+        CPUID_EXTENDED_STATE_MAIN_LEAF_EAX Eax;
+        UINT32 Ebx;
+        UINT32 Ecx;
+        UINT32 Edx;
+    };
+} CPUID_EXTENDED_STATE_MAIN_LEAF_REGS;
+
+// CPUID_EXTENDED_STATE (0x0D)
+// CPUID_EXTENDED_STATE_SUB_LEAF (0x01)
+typedef union
+{
+    INT32 AsInt32[4];
+    struct
+    {
+        CPUID_EXTENDED_STATE_SUB_LEAF_EAX Eax;
+        struct
+        {
+            UINT32 XSaveAreaSize; // The size in bytes of the XSAVE area containing all states enabled by XCRO | IA32_XSS.
+        } Ebx;
+        CPUID_EXTENDED_STATE_SUB_LEAF_ECX Ecx;
+        UINT32 Edx; // Reports the supported bits of the upper 32 bits of the IA32_XSS MSR. IA32_XSS[n + 32] can be set to 1 only if EDX[n] is 1.
+    };
+} CPUID_EXTENDED_STATE_SUB_LEAF_EAX_REGS;
+
+// CPUID_EXTENDED_CPU_SIG (0x80000001)
+typedef union
+{
+    INT32 AsInt32[4];
+    struct
+    {
+        UINT32 Signature;
+        UINT32 ReservedEbx;
+        CPUID_EXTENDED_CPU_SIG_ECX Ecx;
+        CPUID_EXTENDED_CPU_SIG_EDX Edx;
+    } Intel;
+    struct
+    {
+        CPUID_AMD_EXTENDED_CPU_SIG_EAX Eax;
+        CPUID_AMD_EXTENDED_CPU_SIG_EBX Ebx;
+        CPUID_AMD_EXTENDED_CPU_SIG_ECX Ecx;
+        CPUID_AMD_EXTENDED_CPU_SIG_EDX Edx;
+    } Amd;
+} CPUID_EXTENDED_CPU_SIG_REGS;
+
+
+// Additional AMD specific CPUID:
+// See
+// - AMD64 Architecture Programmer’s Manual Volume 2: System Programming (https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24593.pdf)
+// - http://www.flounder.com/cpuid_explorer2.htm#CPUID(0x8000000A)
+// - https://www.spinics.net/lists/kvm/msg279165.html
+// - https://qemu-devel.nongnu.narkive.com/zgmvxGLq/patch-0-3-svm-feature-support-for-qemu
+// - https://github.com/torvalds/linux/blob/28f20a19294da7df158dfca259d0e2b5866baaf9/arch/x86/include/asm/cpufeatures.h#L361
+
+#define CPUID_AMD_SVM_FEATURES 0x8000000A
+
+typedef union
+{
+    struct
+    {
+        UINT SVMRev : 8;     // EAX[7..0]
+        UINT Reserved : 24;  // EAX[31..8]
+    } Bits;
+
+    UINT32    Uint32;
+} CPUID_AMD_SVM_FEATURES_EAX;
+
+typedef union
+{
+    struct
+    {
+        UINT32 NP : 1; // EDX[0] Nested paging support
+        UINT32 LbrVirt : 1; // EDX[1] LBR virtualization
+        UINT32 SVML : 1; // EDX[2] SVM Lock
+        UINT32 NRIPS : 1; // EDX[3] Next RIP save on VMEXIT
+        UINT32 TscRateMsr : 1; // EDX[4] MSR based TSC ratio control
+        UINT32 VmcbClean : 1; // EDX[5] VMCB Clean bits support
+        UINT32 FlushByAsid : 1; // EDX[6] Flush by ASID support
+        UINT32 DecodeAssists : 1; // EDX[7] Decode assists support
+        UINT32 Reserved1 : 2; // EDX[9:8]   Reserved
+        UINT32 PauseFilter : 1; // EDX[10] Pause filter support
+        UINT32 Reserved2 : 1; // EDX[11] Reserved
+        UINT32 PauseFilterThreshold : 1; // EDX[12] Pause filter threshold support
+        UINT32 AVIC : 1; // EDX[13:13] Advanced Virtual Interrupt Controller
+        UINT32 Unknown14 : 1; // EDX[14] Unknown. Described in AMD doc as X2AVIC, but that was probably a typo, since x2AVIC is bit 18.
+        UINT32 VMSAVEVirt : 1; // EDX[15] MSAVE and VMLOAD Virtualization
+        UINT32 VGIF : 1; // EDX[16] Virtual Global-Interrupt Flag
+        UINT32 GMET : 1; // EDX[17] Guest Mode Execute Trap Extension
+        UINT32 x2AVIC : 1; // EDX[18] Virtual x2APIC
+        UINT32 SSSCheck : 1; // EDX[19] AKA SupervisorShadowStack
+        UINT32 V_SPEC_CTRL : 1; // EDX[20] Virtual SPEC_CTRL
+        UINT32 ROGPT : 1; // EDX[21]
+        UINT32 Unknown22 : 1; // EDX[22]
+        UINT32 HOST_MCE_OVERRIDE : 1; // EDX[23]
+        UINT32 TLBSYNC : 1; // EDX[24] TLBSYNC instruction can be intercepted
+        UINT32 VNMI : 1; // EDX[25] NMI Virtualization support
+        UINT32 IbsVirt : 1; // EDX[26] Instruction Based Sampling Virtualization
+        UINT32 LVTReadAllowed : 1; // EDX[27]
+        UINT32 Unknown28 : 1; // EDX[28]
+        UINT32 BusLockThreshold : 1; // EDX[29]
+    } Bits;
+
+    UINT32    Uint32;
+} CPUID_AMD_SVM_FEATURES_EDX;
+
+// CPUID_AMD_SVM_FEATURES (0x8000000A)
+typedef union
+{
+    INT32 AsInt32[4];
+    struct
+    {
+        CPUID_AMD_SVM_FEATURES_EAX Eax;
+        UINT32 NumberOfSupportedASIDs;
+        UINT32 Ecx;
+        CPUID_AMD_SVM_FEATURES_EDX Edx;
+    };
+} CPUID_AMD_SVM_FEATURES_REGS;

sdk/include/reactos/x86x64/Msr.h

@@ -0,0 +1,97 @@
+/*
+ * PROJECT:     ReactOS SDK
+ * LICENSE:     MIT (https://spdx.org/licenses/MIT)
+ * PURPOSE:     Provides CPUID structure definitions
+ * COPYRIGHT:   Copyright 2023 Timo Kreuzer <timo.kreuzer@reactos.org>
+ */
+
+#define SIZE_2KB 2048
+
+#include "Intel/ArchitecturalMsr.h"
+
+typedef struct
+{
+    UINT32 Reserved0 : 2; // [1:0] Reserved
+    UINT32 InterruptWindowExiting : 1; // [2] Interrupt window exiting
+    UINT32 UseTSCOffsetting : 1; // [3] Use TSC offsetting
+    UINT32 Reserved4 : 3; // [6..4] Reserved
+    UINT32 HLTExiting : 1; // [7] HLT exiting
+    UINT32 Reserved8 : 1; // [8] Reserved
+    UINT32 INVLPG_Exiting : 1; // [9] INVLPG exiting
+    UINT32 MWAIT_Exiting : 1; // [10] MWAIT exiting
+    UINT32 RDPMC_Exiting : 1; // [11] RDPMC exiting
+    UINT32 RDTSC_Exiting : 1; // [12] RDTSC exiting
+    UINT32 CR3_Load_Exiting : 1; // [15] CR3 load exiting
+    UINT32 CR3_Store_Exiting : 1; // [16] CR3 store exiting
+    UINT32 ActivateTertiaryControls : 1; // [17] Activate tertiary controls
+    UINT32 CR8_Load_Exiting : 1; // [19] CR8 load exiting
+    UINT32 CR8_Store_Exiting : 1; // [20] CR8 store exiting
+    UINT32 Use_TPR_Shadow : 1; // [21] Use TPR shadow
+    UINT32 NMI_Window_Exiting : 1; // [22] NMI window exiting
+    UINT32 MOV_DR_Exiting : 1; // [23] MOV DR exiting
+    UINT32 Unconditional_IO_Exiting : 1; // [24] Unconditional I/O exiting
+    UINT32 Use_IO_Bitmaps : 1; // [25] Use I/O bitmaps 
+    UINT32 Monitor_Trap_Flag : 1; // [27] Monitor trap flag
+    UINT32 Use_MSR_Bitmap : 1; // [28] Use MSR bitmap
+    UINT32 MONITOR_Exiting : 1; // [29] MONITOR exiting
+    UINT32 PAUSE_Exiting : 1; // [30] PAUSE exiting
+    UINT32 ActivateSecondaryControls : 1; // [31] Activate secondary controls
+} VMX_PROCBASED_CTRLS;
+
+typedef struct
+{
+    UINT32 VirtualizeApicAccesses : 1; // [0] Virtualize APIC accesses 
+    UINT32 EPT : 1; // [1] Enable EPT
+    UINT32 DescriptorTable_Exiting : 1; // [2] Descriptor-table exiting
+    UINT32 RDTSCP : 1; // [3] Enable RDTSCP
+    UINT32 Virtualize_x2APIC : 1; // [4] Virtualize x2APIC mode
+    UINT32 VPID : 1; // [5] Enable VPID
+    UINT32 WBINVD_Exiting : 1; // [6] WBINVD exiting
+    UINT32 UnrestrictedGuest : 1; // [7] Unrestricted guest
+    UINT32 APIC_Virtualization : 1; // [8] APIC-register virtualization
+    UINT32 VirtualInterruptDelivery : 1; // [9] Virtual-interrupt delivery
+    UINT32 PAUSE_Loop_Exiting : 1; // [10] PAUSE-loop exiting
+    UINT32 RDRAND_Exiting : 1; // [11] RDRAND exiting
+    UINT32 INVPCID : 1; // [12] Enable INVPCID
+    UINT32 VM_Functions : 1; // [13] Enable VM functions
+    UINT32 VMCS_Shadowing : 1; //  [14] VMCS shadowing
+    UINT32 ENCLS_Exiting : 1; // [15] Enable ENCLS exiting
+    UINT32 RDSEED_Exiting : 1; // [16] RDSEED exiting
+    UINT32 PML : 1; // [17] Enable PML
+    UINT32 EPT_Violation : 1; // [18] EPT-violation #VE
+    UINT32 Conceal_VMX_from_PT : 1; // [19] Conceal VMX from PT
+    UINT32 XSAVES : 1; // [20] Enable XSAVES / XRSTORS
+    UINT32 PASID_Translation : 1; // [21] PASID translation
+    UINT32 ModeBasedExecutionControl : 1; // [22] Mode-based execute control for EPT
+    UINT32 SubPageWritePerm : 1; // [23] Sub-page write permissions for EPT
+    UINT32 GuestPhysicalAddr : 1; // [24] Intel PT uses guest physical addresses
+    UINT32 TSC_Scaling : 1; // [25] Use TSC scaling
+    UINT32 User_Wait : 1; // [26] Enable user wait and pause
+    UINT32 PCONFIG : 1; // [27] Enable PCONFIG
+    UINT32 ENCLV_Exiting : 1; // [28] Enable ENCLV exiting
+    UINT32 VMM_Bus_Lock_Detection : 1; // [30] VMM bus-lock detection
+    UINT32 InstructionTimeout : 1; // [31] Instruction timeout
+} VMX_PROCBASED_CTLS2;
+
+typedef union
+{
+    struct
+    {
+        VMX_PROCBASED_CTRLS Allowed0;
+        VMX_PROCBASED_CTRLS Allowed1;
+    } Bits;
+
+    UINT64    Uint64;
+} MSR_IA32_VMX_PROCBASED_CTLS_REGISTER;
+
+
+typedef union
+{
+    struct
+    {
+        VMX_PROCBASED_CTLS2 Allowed0;
+        VMX_PROCBASED_CTLS2 Allowed1;
+    } Bits;
+
+    UINT64    Uint64;
+} MSR_IA32_VMX_PROCBASED_CTLS2_REGISTER;

sdk/include/xdk/ketypes.h

@@ -120,9 +120,6 @@ typedef struct _SYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX {
   } DUMMYUNIONNAME;
 } SYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX, *PSYSTEM_LOGICAL_PROCESSOR_INFORMATION_EX;
 
-$endif(_WDMDDK_ || _WINNT_)
-$if(_WDMDDK_)
-
 /* Processor features */
 #define PF_FLOATING_POINT_PRECISION_ERRATA       0
 #define PF_FLOATING_POINT_EMULATED               1
@@ -156,6 +153,21 @@ $if(_WDMDDK_)
 #define PF_ARM_V8_INSTRUCTIONS_AVAILABLE        29
 #define PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE 30
 #define PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE  31
+#define PF_RDTSCP_INSTRUCTION_AVAILABLE         32
+#define PF_RDPID_INSTRUCTION_AVAILABLE          33
+#define PF_ARM_V81_ATOMIC_INSTRUCTIONS_AVAILABLE 34
+#define PF_SSSE3_INSTRUCTIONS_AVAILABLE         36
+#define PF_SSE4_1_INSTRUCTIONS_AVAILABLE        37
+#define PF_SSE4_2_INSTRUCTIONS_AVAILABLE        38
+#define PF_AVX_INSTRUCTIONS_AVAILABLE           39
+#define PF_AVX2_INSTRUCTIONS_AVAILABLE          40
+#define PF_AVX512F_INSTRUCTIONS_AVAILABLE       41
+#define PF_ARM_V82_DP_INSTRUCTIONS_AVAILABLE    43
+#define PF_ARM_V83_JSCVT_INSTRUCTIONS_AVAILABLE 44
+#define PF_ARM_V83_LRCPC_INSTRUCTIONS_AVAILABLE 45
+
+$endif(_WDMDDK_ || _WINNT_)
+$if(_WDMDDK_)
 
 #define MAXIMUM_WAIT_OBJECTS              64
 

sdk/include/xdk/winnt_old.h

@@ -457,40 +457,6 @@
 #define PROCESSOR_ARCHITECTURE_AMD64 9
 #define PROCESSOR_ARCHITECTURE_UNKNOWN 0xFFFF
 
-/* Processor features */
-#define PF_FLOATING_POINT_PRECISION_ERRATA       0
-#define PF_FLOATING_POINT_EMULATED               1
-#define PF_COMPARE_EXCHANGE_DOUBLE               2
-#define PF_MMX_INSTRUCTIONS_AVAILABLE            3
-#define PF_PPC_MOVEMEM_64BIT_OK                  4
-#define PF_ALPHA_BYTE_INSTRUCTIONS               5
-#define PF_XMMI_INSTRUCTIONS_AVAILABLE           6
-#define PF_3DNOW_INSTRUCTIONS_AVAILABLE          7
-#define PF_RDTSC_INSTRUCTION_AVAILABLE           8
-#define PF_PAE_ENABLED                           9
-#define PF_XMMI64_INSTRUCTIONS_AVAILABLE        10
-#define PF_SSE_DAZ_MODE_AVAILABLE               11
-#define PF_NX_ENABLED                           12
-#define PF_SSE3_INSTRUCTIONS_AVAILABLE          13
-#define PF_COMPARE_EXCHANGE128                  14
-#define PF_COMPARE64_EXCHANGE128                15
-#define PF_CHANNELS_ENABLED                     16
-#define PF_XSAVE_ENABLED                        17
-#define PF_ARM_VFP_32_REGISTERS_AVAILABLE       18
-#define PF_ARM_NEON_INSTRUCTIONS_AVAILABLE      19
-#define PF_SECOND_LEVEL_ADDRESS_TRANSLATION     20
-#define PF_VIRT_FIRMWARE_ENABLED                21
-#define PF_RDWRFSGSBASE_AVAILABLE               22
-#define PF_FASTFAIL_AVAILABLE                   23
-#define PF_ARM_DIVIDE_INSTRUCTION_AVAILABLE     24
-#define PF_ARM_64BIT_LOADSTORE_ATOMIC           25
-#define PF_ARM_EXTERNAL_CACHE_AVAILABLE         26
-#define PF_ARM_FMAC_INSTRUCTIONS_AVAILABLE      27
-#define PF_RDRAND_INSTRUCTION_AVAILABLE         28
-#define PF_ARM_V8_INSTRUCTIONS_AVAILABLE        29
-#define PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE 30
-#define PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE  31
-
 /* also in ddk/ntifs.h */
 #define FILE_ACTION_ADDED                   0x00000001
 #define FILE_ACTION_REMOVED                 0x00000002