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x64Emitter: Support YMM registers

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This is accomplished by adding a 0x100 bit the the register.
Made sure that, on AVX instructions, that bit is trucated.
This commit is contained in:
Martino Fontana
2025-09-02 15:11:02 +02:00
parent 033a0540f7
commit 5e69da7eba
2 changed files with 7 additions and 5 deletions
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9
Source/Core/Common/x64Emitter.cpp
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@@ -250,7 +250,7 @@ void OpArg::WriteVEX(XEmitter* emit, X64Reg regOp1, X64Reg regOp2, int L, int pp
int X = !(indexReg & 8);
int B = !(offsetOrBaseReg & 8);
int vvvv = (regOp2 == X64Reg::INVALID_REG) ? 0xf : (regOp2 ^ 0xf);
u8 vvvv = (regOp2 == X64Reg::INVALID_REG) ? 0xf : (regOp2 ^ 0xf);
// do we need any VEX fields that only appear in the three-byte form?
if (X == 1 && B == 1 && W == 0 && mmmmm == 1)
@@ -343,7 +343,7 @@ void OpArg::WriteRest(XEmitter* emit, int extraBytes, X64Reg _operandReg,
if (SIB)
oreg = 4;
emit->WriteModRM(mod, _operandReg & 7, oreg & 7);
emit->WriteModRM(mod, _operandReg, oreg);
if (SIB)
{
@@ -1844,8 +1844,9 @@ void XEmitter::WriteVEXOp(u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, con
{
int mmmmm = GetVEXmmmmm(op);
int pp = GetVEXpp(opPrefix);
// FIXME: we currently don't support 256-bit instructions, and "size" is not the vector size here
arg.WriteVEX(this, regOp1, regOp2, 0, pp, mmmmm, W);
// Note that mixing an XMM register with a YMM register is invalid, which isn't checked here.
int L = (regOp1 != INVALID_REG && regOp1 & 0x100) || (regOp2 != INVALID_REG && regOp2 & 0x100);
arg.WriteVEX(this, regOp1, regOp2, L, pp, mmmmm, W);
Write8(op & 0xFF);
arg.WriteRest(this, extrabytes, regOp1);
}

3
Source/Core/Common/x64Reg.h
View File

@@ -72,7 +72,8 @@ enum X64Reg
XMM14,
XMM15,
YMM0 = 0,
// Use the bit 0x100 to distinguish XMM and YMM registers.
YMM0 = 0x100,
YMM1,
YMM2,
YMM3,